Embodiments of the present invention relate to a method of manufacturing a semiconductor apparatus, and particularly to a method of manufacturing a semiconductor apparatus in which a plurality of semiconductor chips are stacked.
In recent years, the miniaturization and higher-performance of various semiconductor apparatus equipped with electronic equipment have been strongly desired. According to such demands, the technology known as SiP (System in Package), which enables a plurality of semiconductor chips to be contained in one package, has gained attention. In the SiP, a plurality of semiconductor chips with various functions necessary to configure a certain system are equipped. In one example, logic chips that perform operations, such as MPU (Micro-Processing Unit) or SoC (System on Chip), and memory chips that serve as work memories are contained in one package.
In such a case, a vendor of memory chips ships memory chips that have yet to be packaged (unpackaged). This means that the vendor of memory chips needs to test the unpackaged memory chips. As a method of testing the unpackaged memory chips, a method of testing the chips in a wafer state using a wafer tester (probe card) is known.
However, in recent years, with the advent of larger capacities of semiconductor memory and higher-speed data transfer rates, a stacked semiconductor memory in which a plurality of memory chips are stacked has been developed. In the case of such a stacked semiconductor memory, defects could occur in the semiconductor memory not only during a wafer process but also during a stacking process.
Therefore, the manufacturing of the stacked semiconductor memory requires a new test process to detect defects in the stacked semiconductor memory (or a stacked apparatus of semiconductor chips). In particular, as described above, in the case of a stacked semiconductor memory contained in the SiP, a process of testing a stacked apparatus of semiconductor chips that is unpackaged is required. For example, U.S. Patent Application Publication No. 2013/0076384 discloses a method of testing a stacked apparatus of semiconductor chips that is unpackaged.